Semiconductor device manufacturing generally includes various steps of device patterning process. For example, the manufacturing of a semiconductor chip may start with, for example, CAD (computer aided design) generated device patterns and may continue with the effort to replicate these device patterns in a substrate thereupon semiconductor devices are formed. The replication process may involve the use of various exposing techniques, and a variety of subtractive (etching) and additive (deposition) material processing procedures. For example, in a photolithography process, a layer of photo-resist material may be first applied on top of a substrate, and then be selectively exposed according to a pre-determined device pattern. Portions of the photo-resist that are exposed to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.) may experience some changes in their solubility to certain solution. Next, the photo-resist may be developed in a developer solution, thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer, to create a photo-resist pattern. The photo-resist pattern may subsequently be copied or transferred to the substrate underneath the photo-resist pattern.
With continuous scale-down and shrinkage of real estate available for a single semiconductor device, engineers are daily facing the challenge of how to meet the market demand for ever increasing device density. One technique for sub-80 nm pitch patterning is to achieve twice the pattern density through a technique called sidewall image transfer (SIT), also known as sidewall spacer image transfer. However in a conventional SIT process, spacer deposition is performed right after the mandrel litho development. In other words, photo-resist mandrels are first formed, often with the help of an anti-reflective coating (ARC) layer underneath thereof, and material suitable for forming spacers is subsequently deposited to eventually form spacers next to the photo-resist mandrels.
However, concerns and issues have been observed in the above conventional SIT process. For example, imperfection and/or undesired characters have been found in the shapes of above photo-resist mandrels. Such imperfection and/or undesired characters may include, for example, resist footing and slightly tapered profile on the top of the mandrels. In addition to issues relating to the photo-resist mandrels, in the spacer etch-back process of the above conventional process, the etching process is generally not selective to the anti-reflective coating or ARC layer underneath the spacer material layer. As a result, thickness of the ARC layer, after spacer etch-back, often exhibits difference in mandrel-defined trench and spacer-defined trench. Such difference in thickness of ARC layer may result in different shrink at subsequent etch and cause CD (critical dimension) variations, line edge roughness (LER), and pitch walking.